This invention is concerned with variable rate and variable limit dimension controls for a directional enhancement system.
The apparatus of this invention is intended for utilization in a directional enhancement system for quadrophonic decoders such as disclosed in co-pending application Ser. No. 472,291 filed May 22, 1974, now U.S. Pat. No. 3,944,735 and the teachings of U.S. Pat. No. 3,944,735 are incorporated herein by reference.
From one aspect, the invention provides in apparatus for enhancing the directional content of information contained in a plurality of composite signals derived from preceding matrix decoding apparatus, a dimension control comprising: a plurality of limiting devices equal in number to the number of control signals provided in the processor of the directional enhancement system, each having an input-output terminal which is connected to the respective one of said control outputs from said processor, and a control terminal, and operative to limit the maximum value of any control voltage to the voltage present at the control terminal; and a control device having an input and an output, the input being connected to a variable control voltage and the output being connected in common to all of the control terminals of said limiting devices, the whole being operative to limit any control signals which may be developed in the processor to a value less than that which would obtain in the absence of the dimension control, and variable by external means to any desired extent.
From another aspect, the invention provides, in apparatus for enhancing the directional content of information contained in a plurality of composite signals derived from preceding decoding apparatus, a dimension control comprising: voltage-variable resistors equal in number to the number of control signals provided in the directional enhancement system, each having a resistive current path and a control terminal: the resistive current paths each forming part of the discharging devices of the attack-decay control circuits of the processor, and the control terminals being connected in common to an externally variable voltage, the whole being operative to vary by means of the external control the rate of decay of charge of each of the charge storage devices forming part of the attack-decay circuit of the processor of the directional enhancement system.